GAL16V8D-25LP

Product Summary

The GAL16V8D-25LP is a high performance E2CMOS PLD generic array logicTM. The GAL16V8D-25LP at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times(<100ms) allow the device to be reprogrammed quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configurations possible with the GAL16V8 are the PAL architectures listed in the table of the macrocell description section. The GAL16V8D-25LP is capable of emulating any of these PAL architectures with full function/fuse map/parametric compatibility. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.

Parametrics

GAL16V8D-25LP absolute maximum ratings: (1)Supply voltage VCC : –0.5 to +7V; (2)Input voltage applied : –2.5 to VCC +1.0V; (3)Off-state output voltage applied : –2.5 to VCC +1.0V; (4)Storage Temperature : –65 to 150°C; (5)Ambient Temperature with Power Applied : –55 to 125°C.

Features

GAL16V8D-25LP features: (1)HIGH PERFORMANCE E2CMOS&reg; TECHNOLOGY: 3.5 ns Maximum Propagation Delay, Fmax = 250 MHz, 3.0 ns Maximum from Clock Input to Data Output, UltraMOS&reg; Advanced CMOS Technology; (2)50% to 75% REDUCTION IN POWER FROM BIPOLAR: 75mA Typ Icc on Low Power Device, 45mA Typ Icc on Quarter Power Device; (3)ACTIVE PULL-UPS ON ALL PINS:; (4)E2 CELL TECHNOLOGY: Reconfigurable Logic, Reprogrammable Cells, 100% Tested/100% Yields, High Speed Electrical Erasure (<100ms), 20 Year Data Retention; (5)EIGHT OUTPUT LOGIC MACROCELLS: Maximum Flexibility for Complex Logic Designs, Programmable Output Polarity, Also Emulates 20-pin PAL Devices with Full Function/Fuse Map/Parametric Compatibility; (6)PRELOAD AND POWER-ON RESET OF ALL REGISTERS: 100% Functional Testability.

Diagrams